Panasonic Develops First Single-Chip Digital Television Video Decoder


BURLINGTON, NJ (December 18, 1997) — Panasonic AVC American Laboratories, Inc. (PAVCAL) announced today that it has completed development of the world's first single-chip device that will be able to decode digital television video signals and format them for display when America's new, all-digital broadcasting service begins in the fall of 1998.
This low-cost single-chip solution was designed for digital and high definition television (HDTV) receivers, digital set-top boxes that will be used with today's analog TV sets, and computers and other digital products which are being developed now. It is one of the key components in the Digital Television Decoder to be exhibited at Panasonic's booth (N-220) at the Winter Consumer Electronics Show in Las Vegas, January 8-11, 1998.
The major television networks and scores of local broadcast stations are already building new digital facilities, and over-the-air digital TV programs are projected to reach approximately 30% of American households by November 1998, and over 50% by fall 1999.
"This is the first single-chip device that can decode and display all of the digital TV signals that can be broadcast, using the new digital standard, in any of the different HDTV or standard definition formats," said Sai Naimpally, PAVCAL Vice President and leader of its DTV development team. "It processes the digital signals in two ways, both decoding them for display in their original format, and converting them for use in today's televisions."
The new DTV Broadcast Standard gives TV stations the option of using and switching between any of eighteen different television formats, each suited to different purposes. These formats combine different screen ratios (16:9 'wide-screen' or 4:3, like today's TVs), numbers of horizontal and vertical lines of resolution, and scanning methods (either 'interlaced' scanning, like today's TV displays, or 'progressive' scanning, like computer monitors).
The chip--technically termed a "Digital Television MPEG2 Main Profile at High Level Video Decoder"-functions in both a 'full-spec' mode and a 'down-conversion' mode. In the full-spec mode, it decodes the compressed video signal from the broadcast and outputs the original format, that is, either HDTV (1080-lines interlaced or 720-lines progressive) or SDTV (480-lines interlaced or 480-lines progressive). Single chip operation is made possible by use of 500 MHz concurrent 16 Mbit RambusTM DRAM's.
The 'down-conversion' mode converts all compressed video signals to 480-interlaced and 480-progressive formats. This is accomplished by a memory-efficient MPEG down-conversion algorithm developed by PAVCAL.
The operation of the decoder chip conforms to both the DTV Broadcast Standard adopted by the Federal Communications Commission and the more-detailed ATSC DTV Standard, drafted by the all-industry Advanced Television Systems Committee (ATSC).